1. Field of the Invention
This invention relates to integrated circuit manufacture and more particularly to transistors formed on separate elevational levels and interconnect arranged between the transistors to configure a NOR gate.
2. Description of the Relevant Art
The structure and the various components, or features, of a metal oxide semiconductor ("MOS") are generally well known. A MOS transistor typically comprises a substrate material onto which a patterned gate conductor is formed. The gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The impurities placed into the substrate define a junction region, also known as source/drain regions. The gate conductor is patterned from a layer of polysilicon using various lithography techniques.
A typical n-channel MOS (NMOS) transistor employs n-type junctions placed into a p-type substrate. Conversely, a typical p-channel MOS (PMOS) transistor comprises p-type junctions placed into an n-type substrate. The substrate comprises an entire monolithic silicon wafer, of which a portion of the substrate known as a "well" exists. The well is doped opposite the substrate so that it can accommodate junctions of an impurity type opposite the junction in the non-well areas. Accordingly, wells are often employed when both n-type and p-type transistors (i.e., CMOS) are needed.
A pervasive trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To achieve a high density integrated circuit, features such as the gate conductor, source/drain junctions, and interconnect to the junctions must be as small as possible. Many modern day processes employ features which have less than 1.0 .mu.m critical dimension. As feature size decreases, the resulting transistor as well as the interconnect between transistors also decreases. Smaller transistors allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
The benefits of high density circuits can only be realized if advanced processing techniques are used. For example, semiconductor process engineers and researchers often study the benefits of electron beam lithography and x-ray lithography to achieve the lower resolutions needed for submicron features. To some extent wet etch has given way to a more advanced anisotropic (dry etch) technique. Further, silicides and polycides have replaced higher resistivity contact structures mostly due to the lower resistivity needed when a smaller contact area is encountered.
There are numerous other techniques used to achieve a higher density circuit. However, these techniques as well as others still must contend with problems resulting from higher density itself. Even the most advanced processing techniques cannot in all instances offset the problems associated with small features or features arranged extremely close to one another. For example, as the channel length decreases, short channel effects ("SCE") generally occur. SCE cause threshold voltage skews at the channel edges as well as excessive subthreshold currents (e.g., punch through and drain-induced barrier lowering). Related to SCE is the problem of hot carrier injection ("HCI"). As the channel shortens and the supply voltage remains constant, the electric field across the drain-to-channel junction becomes excessive. Excessive electric field can give rise to so called hot carriers and the injection of those carriers into the gate oxide which resides between the substrate (or well) and the overlying gate conductor. Injection of hot carriers should be avoided since those carriers can become trapped and skew the turn-on voltage of the ensuing transistor.
It appears as though even the most advanced processing techniques cannot avoid in all instances the problems which arise as a result of high density fabrication. As features are shrunk and are drawn closer together across a single topological surface, the closeness of those features causes numerous problems even under the most advanced processing conditions. It therefore appears that there may be a certain limitation beyond which feature sizes cannot be reduced if those features are to reside on the single elevational level. It would therefore be desirable to derive a processing technique which can produce features on more than one level. That is, it would be beneficial that this multi-level processing technique produce both active (transistors) and passive (capacitors and resistors) in three dimensions so as to enhance the overall circuit density without incurring harmful side effects associated with feature shrinkage and closeness.
Before a multi-level transistor fabrication process can be introduced, however, the process must pay careful attention to the interconnection between transistors placed on separate levels. Therefore, it is desirable to derive an interconnect scheme which can connect various features on one elevation (topological) level to features on another level. That interconnection must be as short as possible in order to minimize resistance in critical routing conductors between transistors. The desired fabrication process must therefore incorporate not only multi-level fabrication but also high performance interconnect routing as an essential part of that process.
Most logic block portions of an integrated circuit comprise transistors interconnected in various ways. For example, combinatorial logic includes NAND gates, NOR gates, and inverters connected in various ways to achieve the stated logic goal. Associated with each of these structures are at least two transistors whose gates are mutually connected. Thus, it would be desirable to incorporate the transistor pair on separate elevation levels but with a relatively short interconnect shared by the gate inputs to the transistor pair. For example, an inverter arrangement employs a pair of PMOS and NMOS transistors having a single input conductor linking the gate conductors of the transistor pair. Likewise, NAND and NOR generally employ two pairs of PMOS and NMOS transistors, wherein the gate conductors of each pair are linked by a single input conductor. To operate as a high performance input conductor, the resistance and capacitance of that conductor must be as small as possible to lessen the load seen by the upstream circuit.
In addition to limiting the routing length of the single input conductor, it would be of further benefit to use short interconnect at linkages to select transistor junctions. For example, interconnecting a junction of one transistor to a junction of another transistor arranged on an altogether different elevation level would be beneficial if the interconnect were designated as an output conductor. Not only must the output conductor be relatively short for performance reasons, but the conductors (power conductors) routed to power junctions and the conductors (ground conductors) routed to ground junctions must also be short. Therefore, similar to the input conductor linking the input pairs of transistors, conductors used to bring an output from a logic gate, or to couple power or ground to the logic gate must operate under high performance conditions with minimal propagation delay, voltage variance/degradation, etc. Without a mechanism to achieve high speed interconnection at mutually connected gate conductors or at mutually interconnected junctions, multi-level fabrication is limited in its appeal.